Page 162 - DCAP103_Principle of operating system

Unit 5: Memory Management

Notes
Figure 5.5: Paging Model of Logical and Physical Memory

Figure 5.6: Where p is an index into the page table and d is the
displacement within the page

Page number Page offset

p d
m– n n
As a concrete (although minuscule) example, consider the memory in Figure 5.7. Using a page
size of 4 bytes and a physical memory of 32 bytes (8 pages), we show how the user’s view of
memory can be mapped into physical memory. Logical address 0 is page 0, offset 0. Indexing into
the page table, we find that page 0 is in frame 5. Thus, logical address 0 maps to physical address
20 (= (5 × 4) + 0). Logical address 3 (page 0, offset 3) maps to physical address 23 (= (5 × 4)
+ 3). Logical address 4 is page 1, offset 0; according to the page table, page 1 is mapped to
frame 6. Thus, logical address 4 maps to physical address 24 (= (6 × 4) + 0). Logical address
13 maps to physical address 9. You may have noticed that paging itself is a form of dynamic
relocation. Every logical address is bound by the paging hardware to some physical address.
Using paging is similar to using a table of base (or relocation) registers, one for each frame
of memory. When we use a paging scheme, we have no external fragmentation: Any free
frame can be allocated to a process that needs it. However, we may have some internal
fragmentation. Notice that frames are allocated as units. If the memory requirements of a process
do not happen to fall on page boundaries, the last frame allocated may not be completely
full. For example, if pages are 2,048 bytes, a process of 72,766 bytes would need 35 pages

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