Page 76 - DCAP103_Principle of operating system

Unit 3: Process Management-II

contains the complete functionality of what we used to consider a CPU. In traditional symmetric Notes
multiprocessing, each CPU core supports a single hardware instruction thread that interfaces
with the operating system (diagram on left in Figure 3.2). When activating multi-threading,
each core supports multiple hardware instruction threads, each interfacing with the operating
system. Each hardware instruction thread is recognized by the operating system as a logical CPU.

Figure 3.2: Single-threaded SMP and Multi-threaded SMP

Older SMP systems exhibited performance limitations as more CPU’s were added to a
configuration. For those of us familiar with the history of mainframe computers, we saw
that each incremental processor added a lesser amount of additional capacity. In fact, one
vendor, Amdahl Corporation, increased the computational power of the last two processors
in their 12-way computer in order to overcome the SMP shortfall. These limitations resulted
from hardware and operating system architectures designed to ensure data integrity
through the use of various tactics such as signaling and locks. Over the years, all the major
vendors have made significant improvements in this area. As a result, most SMP systems
today have near linear performance scaling in the hardware and operating systems. In a
multiprocessing architecture, there are two approaches to providing additional processing
power. Each additional core, bearing a single logical CPU, delivers a nearly equal quantity
of CPU capacity. In most of today’s architectures, this results in a commensurate increase
in capacity when cores are added. The multi-threading option adds multiple threads to
each core. Each thread adds some additional amount of CPU capacity. However, because
these threads share the CPU core resources, the addition of a thread typically delivers only
a portion of the capacity of a single-threaded core.
Examples of multi-threaded chips include Sun UltraSPARC T1 and T2, SPARC64 VII, Intel Xeon,
Intel Itanium2, Intel Pentium 4, IBM POWER5 and IBM POWER6.

Multi-processor hardware and Symmetric Multi-Processing (SMP) have
become cheap and easily available. There are some powerful trends driving
this change.

3.3.5 Performance Scaling in Multi-threaded Systems
When more threads are added to cores in multi-threaded systems, performance depends upon
chip technologies. All deviate from a linear growth line graph once you get beyond the point
where a single thread is active on each core and core resources are shared. Chip performance
differences as seen during Team Quest testing can be seen in Figure 3.3.

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