Page 74 - DCAP608_REAL TIME SYSTEMS

Unit 7: Commonly used Algorithm to Real-time Scheduling

evaluate for use in our application. A task or ‘thread’ in this context is a sequential execution Notes
stream in a multi-tasking OS.
Key characteristics for a real-time system are

 reliability (stability),
 predictability (it must be deterministic),
 performance (the faster the better),
 compactness to code size (space is money) and

 scalability (one starts with 2 tasks and eventually one ends up with a seven-headed dragon).
The RTOS we are looking at follow the ‘scheduler paradigm’.

Did u know? There are two main levels or categories of execution that can code-execute
logic:

 The interrupt level, and
 The task level

7.1.1 Interrupts and Tasks

An interrupt is an asynchronous exception of which the source is an internal or external hardware
device (note: if the OS supports system calls then software interrupts are possible as well).
Implementation dependent Programmable Interrupt Controllers (PICs) prioritize multiple
interrupt sources so that at any time the highest priority interrupt is presented to the core CPU
for processing.

Did u know? Nesting interrupts refers to the ability of a higher priority interrupt source to
preempt the processing of a lower priority interrupt.

Higher priority interrupt will interrupt the lower priority interrupt, the higher priority interrupt
will run to completion (unless interrupted by a higher priority interrupt), and then the lower
priority interrupt will resume. The above explanation refers to so-called maskable interrupts:
lower priority interrupts are masked (prevented from running) by higher priority interrupts.
Non-maskable interrupts are also possible; these have the highest priority (sometimes even
higher than the RTOS itself) and cannot be prevented from happening.
The performance of an embedded (real-time) system is proportional to:

 the latencies involved with the interrupt, and
 the task handling scheme.
Interrupt latency is the time from when the interrupt request is triggered until the ISR (= the
code of the interrupt service routine) is running. Context information handling (of a task or
interrupt) is additional overhead and increases the latency but should also be deterministic and
known. Task switching latency is the time when a task should be made to ‘run’, involving the
time it takes to store the context information of the running task and restoring the context
information of the to-be-run task.

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