Page 52 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Introduction to Microprocessors

Notes These instructions are 1-byte instructions performing three different tasks. In the first instruction,
both operand registers are specified. In the second instruction, the operand B is specified and the
accumulator is assumed. Similarly, in the third instruction, the accumulator is assumed to be the
implicit operand. These instructions are stored in 8- bit binary format in memory; each requires
one memory location.
MOV rd, rs

rd <— rs copies contents of rs into rd.
Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is the destination
of the data, sss is the code of the source register.

Example: MOV A,B

Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction design of such
processors).
ADD r
A <— A + r

3.4.3 Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the second byte specifies
the operand. Source operand is a data byte immediately following the opcode. For example:
Task Opcode Operand Binary Code Hex Code
Load an 8-bit MVI A, Data 0011 1110 3E First Byte
data byte in the Data Second Byte
DATA
accumulator.
Assume that the data byte is 32H. The assembly language instruction is written as
Mnemonics Hex Code

MVI A, 32H 3E 32H
The instruction would require two memory locations to store in memory.
MVI r,data
r <— data

Example: MVI A, 30H coded as 3EH 30H as two contiguous bytes. This is an example of

immediate addressing.
ADI data
A <— A + data
OUT port

where port is an 8-bit device address. (Port) <— A. Since the byte is not the data but points
directly to where it is located this is called direct addressing.

3.4.4 Three-Byte Instructions

In a three-byte instruction, the first byte specifies the opcode, and the following two bytes specify
the 16-bit address. Note that the second byte is the low-order address and the third byte is the
high-order address.
opcode + data byte + data byte

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