Page 65 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Unit 4: Microprocessor Architecture

features of a microprocessor are so small that they are dwarfed by the smallest speck of dust; Notes
thus, the chips must be manufactured in a highly controlled, dust-free environment.

4.2.8 Multi-core Architecture

Microprocessor architecture has traditionally consisted of a single “core”; that is, the chips could
only process one piece of information at a time. However, many processors are now being built
with two, four, or even more cores, allowing one microprocessor to process multiple pieces of
information simultaneously.

4.2.9 Von Neumann Architecture

Early computer programs were hard-wired. To reprogram a computer meant changing the
hardware switches manually, that took a long time with potential errors. Computer memory was
only used for storing data.
A Von Neumann microprocessor is a processor that follows this pattern:
Fetch: An instruction and the necessary data are obtained from memory.

Decode: The instruction and data are separated, and the components and pathways required to
execute the instruction are activated.
Execute: The instruction is performed, the data is manipulated, and the results are stored.

This pattern is typically implemented by separating the task into two components, the control,
and the data path.

Draw the block diagram of Von Neumann Architecture.

Control: The control unit reads the instruction, and activates the appropriate parts of the data
path.

4.2.10 Data Path
The data path is the pathway that the data takes through the microprocessor. As the data travels
to different parts of the data path, the command signals from the control unit cause the data to be
manipulated in specific ways, according to the instruction. The data path consists of the circuitry
for transforming data and for storing temporary data. It contains ALUs capable of transforming
data through operations such as addition, subtraction, logical AND, OR, inverting, and shifting.
4.2.11 Harvard Architecture

In a Harvard Architecture machine, the computer system’s memory is separated into two discrete
parts: data and instructions. In a pure Harvard system, the two different memories occupy separate
memory modules, and instructions can only be executed from the instruction memory.
In a “Princeton Architecture” machine, the computer system’s memory comprises one uniform
address space: data and instructions may be placed anywhere in this single memory.
Many DSPs are modified Harvard architectures, designed to simultaneously access three distinct
memory areas: the program instructions, the signal data samples, and the filter coefficients (often
called the P, X, and Y memories).
In theory, such three-way Harvard architectures can be three times as fast as a Princeton architecture
that is forced to read the instruction, the data sample, and the filter coefficient, one at a time.
In Princeton architecture systems, there is only one memory area. Any particular memory location
that can be written to and read as data at any one time can also be executed as an instruction at

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