Page 184 - DCAP103_Principle of operating system

Unit 5: Memory Management

instruction. One solution is to create a new special status register to record the register number Notes
and amount modified for any register that is changed during the execution of an instruction. This
status register allows the operating system to undo the effects of a partially executed instruction
that causes a page fault. These are by no means the only architectural problems resulting from
adding paging to an existing architecture to allow demand paging, but they illustrate some of
the difficulties. Paging is added between the CPU and the memory in a computer system. It
should be entirely transparent to the user process. Thus, people often assume that paging could
be added to any system. Although this assumption is true for a non-demand-paging environment,
where a page fault represents a fatal error, it is not true where a page fault means only that an
additional page must be brought into memory and the process restarted.
5.9.2 Performance of Demand Paging
Demand paging can have a significant effect on the performance of a computer system. To see
why, let us compute the effective access time for a demand paged memory. For most computer
systems, the memory-access time, denoted ma, now ranges from 10 to 200 nanoseconds. As
long as we have no page faults, the effective access time is equal to the memory access time.
If, however, a page fault occurs, we must first read the relevant page from disk, and then
access the desired word. Let p be the probability of a page fault (0 5 p 5 1). We would expect
p to be close to zero; that is, there will be only a few page faults. The effective access time is
then effective access time = (1 – p) x ma + p x page fault time. To compute the effective access
time, we must know how much time is needed to service a page fault. A page fault causes the
following sequence to occur:
1. Trap to the operating system.
2. Save the user registers and process state.
3. Determine that the interrupt was a page fault.

4. Check that the page reference was legal and determine the location of the page on the
disk.
5. Issue a read from the disk to a free frame:

(a) Wait in a queue for this device until the read request is serviced.
(b) Wait for the device seek and/or latency time.
(c) Begin the transfer of the page to a free frame.
6. While waiting, allocate the CPU to some other user (CPU scheduling; optional).

7. Interrupt from the disk (I/O completed).
8. Save the registers and process state for the other user (if step 6 is executed).
9. Determine that the interrupt was from the disk.
10. Correct the page table and other tables to show that the desired page is now in memory.
11. Wait for the CPU to be allocated to this process again.

12. Restore the user registers, process state, and new page table, then resume the interrupted
instruction.
Not all of these steps are necessary in every case. For example, we are assuming that, in step
6, the CPU is allocated to another process while the I/O occurs. This arrangement allows
multiprogramming to maintain CPU utilization, but requires additional time to resume the
page-fault service routine when the I/O transfer is complete.

In any case, we are faced with three major components of the page-fault service time:

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