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Unit 10: Working of Clock-driven Scheduling




                                                                                                Notes
                            Figure 10.2: Example of Scheduling Sporadic Jobs























          Source:  ansari.szabist-isb.edu.pk/RTS/RTS0508.ppt
          At time 16 acceptance test is done, the scheduler finds only 4.5 units of time available in frames
          before the deadline of S4, after accounting the slack time already committed to the remaining
          portions of S2 and S3, therefore it is rejected. When the remaining portion of S3 completes in the
          current frame, S2 executes until the beginning of the next frame. The last portion of S2 executes
          in frames 6 and 7.

          Self Assessment

          State whether the following statements are True or False:
          7.   Like jobs in periodic tasks, sporadic jobs have soft deadlines.

          8.   A sporadic job that activates robotic arm is released when a defective part is detected.
          9.   The arm, when activated, removes the part from the conveyor belt.
          10.  The scheduler accepts the new job only if no sporadic jobs in system are adversely affected.

          11.  The scheduler maintains a queue of accepted sporadic jobs in non-decreasing order of
               their deadlines and inserts each newly accepted sporadic job into this queue in this order.
          12.  Whenever a server or job completes the cyclic executive wakes up to execute.


              

             Case Study  6-STAGE FPU


                   lock scheduling is proposed on the premise that typical workloads exhibit a high
                   degree of cycle-level variations in activity due to intermittent bubbles that persist
             Cin the instruction streams. In order to verify this premise, this section presents a
             brief case study of the characteristics of workloads found in the SPECfp benchmark suite
             running on a FPU like that found in IBM’s POWER4.
             We assume a FPU that consists of two parallel pipelines with each consisting of 6 pipeline
             stages divided by FFs, as shown in Figure. 1(a). Data enters the pipelines through FF0.
                                                                                 Contd...



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