Page 229 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design

Notes connected in parallel to each converter. The proper converter is then selected for decoding by
the select lines.

The second method involves the use of only one D/A converter and switching its output. This is
called multiplexing, and such a system is shown in Figure 12.14b.

An OA connected as in Figure 12.15a is a unity-gain non-inverting voltage amplifier, that is
V = V . Two such OAs are used with a capacitor in Figure 12.15b.
0 i
Figure 12.15: (a) Unity gain amplifier, (b) Sample-and-hold Circuit

Steady-state: Sample-and-hold amplifier. When the switch is closed, the capacitor charges to
the D/A.
Accuracy test: Converter output voltage. When the switch is opened, the capacitor holds the voltage
level until the next sampling time. The operational amplifier provides large input impedance.
Monotonicity test: So as not to discharge the capacitor appreciably and at the same time offers
gain to drive external circuits.

When the D/A converter is used in conjunction with a multiplexer, the maximum rate at which
the converter can operate must be considered. Each time data is shifted into the register, transients
appear at the output of the converter. This is due mainly to the fact that each flip-flop has different
rise and fall times. Thus a settling time must be allowed between the time data is shifted into
the register and the time the analog voltage is read out. This settling time is the main factor in
determining the maximum rate of multiplexing the output. The worst case is when all bits change
(e.g. from 1000 to 0111).
Naturally, the capacitors on the sample-and-hold amplifiers are not capable of holding a voltage
indefinitely; therefore, the sampling rate must be sufficient to ensure that these voltages do not
decay appreciably between samples. The sampling rate is a function of the capacitors as well as
the frequency of the analog signal which is expected at the output of the converter.

At this point, you might be curious to know just how fast a signal must be sampled in order to
preserve its integrity. Common sense leads to the conclusion that the more often the signal is
sampled, the less the sample degrades between samples. On the other hand, if too few samples
are taken, the signal degrades too much (the sample-and-hold capacitors discharge too much),
and the signal information is lost. We would like to reduce the sampling rate to the minimum
necessary to extract all the necessary information from the signal. The solution to this problem
involves more than we have time for here, but the results are easy enough to apply.
First, if the signal in question is sinusoidal, it is necessary to sample at only twice the signal
frequency. For instance, if the signal is a 5-kHz sine wave, it must be sampled at a rate greater than
or equal to 10 kHz. In other words, a sample must be taken every 1/10000 s = 100 µs. What if the
waveform is not sinusoidal? Any waveform that is periodic can be represented by a summation
of sine and cosine terms, with each succeeding term having a higher frequency. In this case, it
will be necessary to sample at a rate equal to twice the highest frequency of interest.

12.3.2 D/A Converter Testing
Two simple but important tests that can be performed to check the proper operation of the D/A
converter are the steady-state accuracy test and the monotonicity test.

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