Page 201 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Unit 14: Interrupts

14.5 Summary Notes

• Interrupt is a signal send by external device to the processor so as to request the processor to
perform a particular work.

• In the 8085 microprocessor are eight data lines, D through D .
0 7
• Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store
operations.
• Flag is an 8-bit register containing 5 1-bit flags: Sign - set if the most significant bit.

14.6 Keywords

INTR: INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor
fetches from the bus one instruction.
RST5.5: RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 2Ch (hexadecimal) address.
RST6.5: RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 34h (hexadecimal) address.

RST7.5: RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 3Ch (hexadecimal) address.

Trap: Trap is a non-maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 24h (hexadecimal) address.

1. Give the instructions that perform the logical operations.
2. Draw the block diagram of CPU architecture.

14.7 Self-Assessment Questions

1. INTR stand for ………….
(a) Interrupt Request (b) Interrupt Acknowledge

(c) Interrupt Enable (d) Internet Request
2. INTA stand for ………….
(a) Interrupt Request (b) Interrupt Acknowledge

(c) Interrupt Enable (d) Internet Request
3. INTE stand for ………….
(a) Interrupt Request (b) Interrupt Acknowledge
(c) Interrupt Enable (d) Internet Request

4. The 8085 has facilities for servicing interrupts similar to the ………….
(a) 8086 (b) 8087
(c) 8080 (d) 8085

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