Page 196 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Introduction to Microprocessors

Notes The 8085 has 5 interrupt inputs:

1. The INTR input.
2. The INTR input is the only non-vectored interrupt.
3. INTR is maskable using the EI/DI instruction pair.

4. RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
5. RST 5.5, RST 6.5, and RST 7.5 are all maskable.
6. TRAP is the only non-maskable interrupt in the 8085.
7. TRAP is also automatically vectored.

An interrupt vector is a pointer to where the ISR is stored in memory.
All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector
Table (IVT). The IVT is usually located in memory page 00 (0000H - 00FFH). The purpose of the
IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt
arrives.

Example: Let, a device interrupts the Microprocessor using the RST 7.5 interrupt line.

Because the RST 7.5 interrupt is vectored, Microprocessor knows, in which memory location it
has to go using a call instruction to get the ISR address. RST7.5 is knows as Call 003Ch to
Microprocessor. Microprocessor goes to 003C location and will get a JMP instruction to the actual
ISR address. The Microprocessor will then, jump to the ISR location.

The 8085 Non-Vectored Interrupt Process
1. The interrupt process should be enabled using the EI instruction.

2. The 8085 checks for an interrupt during the execution of every instruction.
3. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA
(Interrupt acknowledge) signal to the device that interrupted.

4. INTA allows the I/O device to send a RST instruction through data bus.
5. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the
stack and the program is transferred to 'call' location (ISR Call) specified by the RST instruction.
6. Microprocessor Performs the ISR.
8. ISR must include the 'EI' instruction to enable the further interrupt within the program.

Stack pointer is a 16 bit register. This register is always incremented /
decremented by 2.

14.3 Interrupt 8085 Microprocessor

The 8085 microprocessor has 5 interrupts. They are presented below in the order of their priority
(from lowest to highest):
INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches
from the bus one instruction, usually one of these instructions:
• One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter
into stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7
supplied with the RST instruction).

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