Page 194 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Introduction to Microprocessors

Notes NAME: ADDRESS:

RST 0 00H
RST 1 08H
RST 2 10H
RST 3 18H
RST 4 20H

TRAP 24H
RST 5 28H
REST 5.5 2CH
RST 6 30H
RST 6.5 34H
RST 7 38H
RST 7.5 3CH

The normal vectors for the Restart instructions 0 through 7, as created by the 8214.
They are 8 bytes apart, which is ample room for such jumps as are needed to obtain
the interrupt servicing routines.

Now look at the bold face items. These items have vector areas which are between the original
vectors in RAM. 12he 5.5, for instance, is half way between the RST 5 and the RST 6 vectors, hence
the “0.5”. If all the vectors were in use, those located above address 20H would each have only four
bytes in which to locate and jump to the interrupt service routine. This should be enough room,
however, if used wisely. Note also that the Trap interrupt is located at the 4.5 point in the vectors.
The 5.5, 6.5, and 7.5 vectors have several items in common. First, they each have their own pin
directly into the 8085. These pins will accept asynchronous interrupt requests without the need
for any sort of external priority interrupt device. Secondly, these interrupts are individually
makeable. This is accomplished via the Set Interrupt Mask instruction. This instruction allows
bits to be set or cleared which will permit or deny an interrupt on one of these lines to force the '85
into an interrupt service cycle. When an input is received on one of these lines and its respective
mask bit is enabled (set to 0), the processor will finish the current machine cycle, then enter a
interrupt service cycle in which an automatic jam inside the MP will vector it to 2CH, 34H, or
3CH for 5.5, 6.5, or 7.5 respectively. Those locations will assumedly have been previously set to
contain directions to the interrupt servicing routines.
The RST 5.5 and RST 6.5 interrupts are "level sensitive" This means that the device wishing to
interrupt will apply a steady high level to the appropriate pin and hold it there until the 8085 gets
around to responding. When the '85 recognizes the applied high level, it will permit the interrupt
to be serviced in the next machine cycle. The mask bits set by the SIM instruction will directly
determine what the RIM instruction sees with respect to the 5.5 and 6.5 interrupt pending bits. If
the mask bits are set high (to a 1), these interrupts are masked off. This means that a following
RIM will not see them as pending. If the mask bits are set to 0 (enabled), a RIM will see the true
condition in bits 4 and 5 of the mask byte.
The RST 7.5 interrupt is "edge sensitive". This means that a pulse applied to this pin, requesting
an interrupt, can come and go before the processor gets around to servicing it. This is possible
because, unlike the 5.5 and 6.5, the 7.5 has a flip-flop just inside its pin which instantly registers
the fact that an interrupt request, albeit short, was applied to the device. This flip-flop provides a
bit which is read in RIM instruction as bit 6. This bit will indicate an interrupt pending if a quick

188 LOVELY PROFESSIONAL UNIVERSITY