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Introduction to Microprocessors


                  Notes          Pressed or when the mouse is moved. Software interrupts are generated by a program requiring
                                 disk input or output.
                                 An internal timer may continually interrupt the computer several times per second to keep the

                                 Time of day current or for time sharing purposes. When an interrupt occurs, control is transferred
                                 to the operating system, transferred to the operating system, which determines the action to be
                                 taken. Interrupts are prioritized; the higher the priority, the faster the interrupt will be serviced
                                 Basically, a single computer can perform only one computer instruction at a time. But, because it
                                 can be interrupted, it can take turns in which programs or sets of instructions that it performs.
                                 This is instructions that it performs. This is known as multitasking.
                                 An operating system usually has some code that is called an interrupt handler. The interrupt
                                 handler prioritizes the interrupts and saves them in a queue if more than one is waiting to be
                                 handled.

                                 The operating system has another little program, sometimes called a scheduler. The operating
                                 system has another little program, sometimes called a scheduler.

                                 14.1 8085 Interrupts


                                 Interrupt is a process where an external device can get the attention of the microprocessor. The
                                 process starts from the I/O device and is asynchronous.

                                 Interrupts in 8085 microprocessor are classified into Hardware interrupts and Software interrupts.
                                 1. Hardware interrupt - TRAP, RST7.5, RST6.5, RST5.5, and INTR.
                                 2. Software interrupt - RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7.

                                 Intel 8085 microprocessor is the next generation of Intel 8080 CPU family. In addition to being
                                 faster than the 8080, the 8085 had the following enhancements:
                                 •  Intel 8085 had single 5 Volt power supply.

                                 •  Clock oscillator and system controller were integrated on the chip.
                                 •  The CPU included serial I/O port.
                                 •  Two new instructions were added to 8085 instruction set.
                                 The CPU also included a few undocumented instructions. These instructions were supposed to
                                 be a part of the CPU instruction set, but at the last moment they were left undocumented because
                                 they were not compatible with forthcoming Intel 8086.

                                                Interrupt is a signal send by external device to the processor so as to request
                                                the processor to perform a particular work.


                                 14.2 Type 8085 Interrupts

                                 The 8085 has facilities for servicing interrupts similar to the 8080. The functional items required
                                 are an Interrupt Request (INTR) pin, an Interrupt Acknowledge (INTA) pin, an Interrupt Enable
                                 (INTE) pin; eight interrupt vectors in low RAM, and the Restart instruction. These perform in the
                                 same way as the 8080 interrupt system. Here is a brief review:
                                 1. A program is running normally in the system. The 8214 Priority Interrupt Controller or similar
                                    circuit has its compare mask set to some priority level. The Interrupt Enable bit has been set
                                    on by some previous routine, enabling interrupts.




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