Page 195 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Unit 14: Interrupts

pulse is applied to pin 7.5, even though bit 2 of the SIM instruction, the 7.5 mask bit, is turned on Notes
(disabled). Bit 2 of SIM byte, therefore, acts differently as a mask bit than does bits 0 and 1 for 5.5
and 6.5. Whereas bits 0 and 1 will mask off all indication of action on pins 5.5 and 6.5, bit 2 will
allow the indication of a 7.5 interrupt pending, but will prevent the actual servicing of the 7.5
vector unless the mask is enabled for it. In this way, even though the mask set by the SIM prevents
the MP from servicing a 7.5 interrupt, the fact that such an interrupt did occur, captured by the
flip-flop, and is indicated to whatever routine next executes a RIM instruction.
While the normal interrupt and 5.5 and 6.5 interrupts' enable bits are reset when these are serviced,
the 7.5 interrupt flip-flop must be turned off individually. This may be accomplished by actually
responding to the interrupt, just like the other interrupts above; by having the 8085 receiving a /
RESET IN, which would also reset the whole system; or by executing a SIM instruction in which
bit 4 of the SIM byte is set on. This bit 4 is the "Reset RST 7.5" bit, and will reset the flip-flop if it is
on when a SIM is executed.

Differentiate between RAM and ROM.

14.2.2 Non-maskable Interrupt

The Trap instruction is a non-maskable interrupt provision for the 8085. There is no mask bit
related to it, and no control bits of any kind. It is used for interrupts of a catastrophic nature, such
as the impending doom of a power failure. It is essentially an edge-sensitive input, since its pin
connects directly inside the '85 to a flip-flop to capture the fact that a request was made. However,
the inside circuitry around the flip-flop requires that although the flip-flop is set, the asserted
level be continually applied thereafter until the processor enters the service cycle. This is shown
in a diagram in the documentation. The Trap, therefore, is called both edge-sensitive and level
sensitive as well. The order of priority for all of the interrupts of the 8085, from least important to
most important, are the Restart 0 through Restart 7, RST 5.5, RST 6.5, RST 7.5, and finally the
Trap. Remember that through the use of the 8214, the RST 0 through 7 interrupts are also prioritized,
with 0 as the least important and 7 as the most important. Collectively, the 8085 has a complete
set of interrupt capabilities that should serve every need.
When the Microprocessor receives an interrupt signal, it suspends the currently executing program
and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each
interrupt will most probably have its own ISR.
Responding to an interrupt may be immediate or delayed depending on whether the interrupt is
maskable or non-maskable and whether interrupts are being masked or not.
There are two ways of redirecting the execution to the ISR depending on whether the interrupt is
vectored or non-vectored.
Vectored: The address of the subroutine is already known to the Microprocessor
Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor

When a device interrupts, it actually wants the MP to give a service which is equivalent to asking
the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine)

1. The 'EI' instruction is a one byte instruction and is used to Enable the non-
maskable interrupts.
2. The 8085 has a single Non-Maskable interrupt. The non-maskable interrupt
is not affected by the value of the Interrupt Enable flip flop.

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