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Unit 14: Interrupts

2. A device wishes to interrupt the system. It raises its own line which connects directly to the Notes
8214. The 8214 compares this request with the current status of the system. If the new request
is higher in priority than the existing (if any), the interrupt will be allowed. If not, the interrupt
will be latched for later use, but no further action is taken.
3. The Interrupts Enabled line exiting the 8085 is high, indicating that interrupts are permitted.
The 8214 raises the Interrupt line, which causes the MP to finish the current instruction, and
then enter an interrupt service cycle. The MP generates the Interrupts Acknowledge line at
the beginning of this cycle to permit the 8214 to proceed.
4. Upon receipt of the INTA line, the 8214 along with an 8212 octal latch or similar circuit,
generates a Restart instruction which it jams onto the data bus at T3 of the interrupt service
cycle. The MP receives this, and removes from it the three-bit modulo-8 vector, which it then
multiplies by 8 to find the vector in low RAM. This vector contains one or more instructions
which can service the device causing the interrupt.

5. The execution of the Restart instruction causes the address of the next normal instruction to
be executed, obtained from PC, to be placed onto the stack. The next machine cycle will be the
M1 of the instruction located in the vector in low RAM. This instruction can now guide the
MP to the routine to service the interrupt.
6. At the end of the interrupt service routine, a Return (RTN) instruction will cause the popping
of the address off the stack which was of the next instruction to be serviced if the interrupt
had not occurred.
The system now finds itself back where it came from

There are three possible variations to the above scenario. First, unlike the 8080, the 8085 will
permit the interrupt as described above as long as no other interrupts are pending which are of
greater importance. These, of course, are the 5.5, 6.5, 7.5, and Trap. If any of these are pending,
they will be serviced first.
Secondly, while the 8214 was the original device to service interrupts on the 8080 system, the
8085 can work with the 8259A Programmable Interrupt Controller as well. This is a more complex
device, programmable as to how it handles interrupts, and stackable to two levels, providing as
many as 64 levels of interrupt for the '85. The 8259A, moreover, generates Call instructions as
well as Restarts. This means that a Call may be jammed onto the data bus during T3 of the interrupt
cycle, instead of Restart. While the Restart provides a vector to eight different places in low RAM,
depending upon the modulo-8 bits it contains, the Call contains a full two-byte-wide address,
which can effectively vector the MP to any-place within the 64K RAM address space. This
obviously provides a vastly extended ability to handle interrupts more efficiently.
The third item to be aware of is that the Interrupt Enable flip-flop of the 8080 is now observable as
the IE bit #3 of the byte obtained by executing the RIM instruction. It hitherto has not been available,
and its status must be remembered by the programmer. Now the bit may be checked with the
RIM instruction.
Interrupts can be classified into two types:
1. Makeable Interrupts (Can be delayed or rejected)

2. Non-makeable Interrupts (Cannot be delayed or rejected)

14.2.1 Makeable Interrupts

Three maskable interrupts are provided in the 8085, each with their own pins. They are named
RST 5.5, RST 6.5, and RST 7.5, respectively. To see where these names come from, study this chart

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