Page 174 - DCAP403_Operating System

Unit 9: I/O & Secondary Storage Structure

lines would also pass through this logic. In some cases, the bus control lines may pass through Notes
the handshaking logic unaltered (i.e. be connected directly to the main interface device).
The address decoder must receive the address and perhaps a bit indicating wheteher the address
is in the I/O address space or the memory address space. In a minimum mode system this bit
could be taken from the M/IO (or IO/M) line, but in a maximum mode system the memory-I/O
determination is obtained directly from the IOWC and IORC lines. If the decoder determines that
its interface is being referenced, then the decoder must send signals to the main device indicating
that it has been selected and which register is being accessed. The bits designing the register may
be the low-order address bits, but are often generated inside the interface device from the read/
write control signal as well as the address signals.

Example: If there are two registers A and B that can be read from and two registers C and
D that can be written into, then the read and write signals and bit 0 of the address bus could be
used to specify the register as follows:
Write Read Address Bit 0 Register Being Accessed
0 1 0 A
0 1 1 B
1 0 0 C
1 0 1 D
If a daisy chain is included in the system instead of an interrupt priority management device, then
each interface must contain daisy chain logic; and must include logic to generate the interrupt
type. Also, the interface may be associated with a DMA controller.
Many interface are designed to detect at least two kinds of errors. Because the lines connecting
an interface to its device are almost subject to noise, parity bits are normally appended to the
information bytes as they are transmitted. If even parity is used the parity bit is set so that the
total number of 1s, including the parity bit, is even. For odd parity the total number of 1s is odd.
As these bytes are received the parity is checked and if it is in error, a certain status bit is set in a
status register. Some interfaces are also designed to check error detection redundancy bytes that
are placed after blocks of data. The other type of error most interfaces can detect is known as an
overrun error. As we have seen when a computer inputs data it brings the data in form a data-in
buffer register. If, for some reason, the contents of this register are replaced by new data before
they are input by the computer, an overrun error occurs, such an error also happens when data
are put in a data-out buffer before the current contents of the register have been output. As with
parity errors, overrun errors cause a certain status bit to be set.

9.4 Functions of I/O Interface

An I/O interface is bridge between the processor and I/O devices. It controls the data exchange
between the external devices and the main memory; or external devices and processor registers.
Therefore, an I/O interface provides an interface internal to the computer which connects it to the
processor and main memory and an interface external to the computer connecting it to external
device or peripheral. The I/O interface should not only communicate the information from
processor to main I/O device, but it should also coordinate these two. In addition, since there
are speed differences between processor and I/O devices, the I/O interface should have facilities
like buffer and error detection mechanism. Therefore, the major functions or requirements of an
I/O interface are:

It should be able to provide control and timing signals

The need of I/O from various I/O devices by the processor is quite unpredictable. In fact it
depends on I/O needs of particular programs and normally does not follow any pattern. Since, the

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