Page 175 - DCAP403_Operating System

Operating System

Notes I/O interface also shares system bus and memory for data input/output, control and timing are
needed to coordinate the flow of data from/to external devices to/from processor or memory.

Example: The control of the transfer of data from an external device to the processor
might involve the following steps:
1. The processor enquires from the I/O interface to check the status of the attached device.
The status can be busy, ready or out of order.
2. The I/O interface returns the device status.
3. If the device is operational and ready to transmit, the processor requests the transfer of
data by means of a command, which is a binary signal, to the I/O interface.
4. The I/O interface obtains a unit of data (e.g., 8 or 16 bits) from the external device.
5. The data is transferred from the I/O interface to the processor.

It should Communicate with the Processor

The above example clearly specifies the need of communication between the processor and I/O
interface. This communication involves the following steps:
1. Commands such as READ SECTOR, WRITE SECTOR, SEEK track number and SCAN
record-id sent over the control bus.
2. Data that are exchanged between the processor and I/O interface sent over the data bus.
3. Status: As peripherals are so slow, it is important to know the status of the I/O interface.
The status signals are BUSY or READY or in an error condition from I/O interface.
4. Address recognition as each word of memory has an address, so does each I/O device.
Thus an I/O interface must recognize one unique address for each peripheral it controls.

It should Communicate with the I/O Device

Communication between I/O interface and I/O device is needed to complete the I/O operation.
This communication involves commands, status or data.

It should have a Provision for Data Buffering

Data buffering is quite useful for the purpose of smoothing out the gaps in speed of processor
and the I/O devices. The data buffers are registers, which hold the I/O information temporarily.
The I/O is performed in short bursts in which data are stored in buffer area while the device can
take its own time to accept them. In I/O device to processor transfer, data are fi rst transferred
to the buffer and then passed on to the processor from these buffer registers. Thus, the I/O
operation does not tie up the bus for slower I/O devices.

Error Detection Mechanism should be in-built

The error detection mechanism may involve checking the mechanical as well as data
communication errors. These errors should be reported to the processor. The examples of the
kind of mechanical errors that can occur in devices are paper jam in printer, mechanical failure,
electrical failure etc. The data communication errors may be checked by using parity bit.

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