Page 176 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 10: Clocked Sequential Circuits

10.3.2 State Table Notes
The state table is the same as the excitation table of a flip-flop, i.e. what inputs need to be applied
to get the required output. In other words this Table 10.8 gives the inputs required to produce
the specific outputs.
Table 10.8: State Table

Q1 Q0 Q1+ Q0+ T1 T0
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1
10.3.3 K-map

The K-map is the same as the combinational circuits K-map. Only difference: we draw K-map for
the inputs, i.e. T1 and T0 in the Table 10.8. From the Table 10.8 we deduct that we do not need
to draw K-map for T0, as it is high for all the state combinations. But for T1 we need to draw the
K-map as shown below, using SOP.
Figure 10.12: K-map

10.3.4 Circuit

There is nothing special in drawing the circuit; it is the same as any circuit drawing from K-map
output. Below is the circuit of 2-bit up counter using the T flip-flop.

Figure 10.13: Circuit

Before design any circuit it must be carefully analyzed to ensure that it
converges to some valid state.

10.4 State Minimization

Minimizing states is of interest because fewer states implies fewer flip-flops to implement the
circuit (Complexity of combinational logic may also be reduced). Instead of trying to show which
states are equivalent, it is often easier to show which states are definitely not equivalent (This
can be exploited to define a minimization procedure). For simple FSMs, it is easy to see from the

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