Page 183 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design

Notes The Figure 10.19 shows two possible assignments. Both assign S0 to 00 and place S3’ and S4’
adjacent to each other.
Let us consider more complicated case.
Figure 10.20: The State Diagram of the 4-bit String Recognizer

Reset
S0
0/0 1/0

S1 S2
1/0 1/0
0/0 0/0

S3’ S4’

0, 1/0 0/0 1/0

S7’ S10’

0, 1/0 0/1 1/0

Applying the guidelines yields the following set of assignment constraints:
Highest priority : (S3’, S4’), (S7’, S10’);

Medium priority : (S1, S2), (S3’, S4’), (S7’, S10’);
Lowest priority : 0/0: (S0, S1, S2, S3’, S4’, S7’);

1/0 : (S0, S1, S3’, S4’, S7’, S10’);
The Figure 10.20 shows two alternative assignments that meet most of these constraints:
Figure 10.21: Two Alternative Assignments

Q1Q0 Q1Q0
00 01 11 10 Q2 00 01 11 10
Q2
0 S0 0 S0
1 1

Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 S0 S3′ 0 S0

1 S4′ 1 S7′ S10′

Q1Q0 Q1Q0
00 01 11 10 00 01 11 10
Q2 Q2
0 S0 S3′ S7′ 0 S0 S3′
1 S4′ S10′ 1 S7′ S4′ S10′
Contd...

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