Page 37 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design

Notes Table 2.9: Symbol and Truth Table

Symbol Truth Table
Enable A Q
1 0 0
1 1 1
0 0 Hi-Z
Tri-state Gate
0 1 Hi-Z
Read as Output = Input if Enable is equal to “1”

An Active-high tri-state gate is activated when a logic level “1” is applied to its “enable” control
line and the data passes through from its input to its output. When the enable control line is at
logic level “0”, the gate output is disabled and a high impedance condition, Hi-Z, is present on
the output.

2.2.1 Active “LOW” Tri-state Gate
Table 2.10: Symbol and Truth Table

Symbol Truth Table
Enable A Q
0 0 0
0 1 1

Tri-state Gate 1 0 Hi-Z
1 1 Hi-Z
Read as Output = Input if Enable is NOT equal to “1”

An Active-low Tri-state Gate is the opposite to the above, and is activated when a logic level “0”
is applied to its “enable” control line. The data passes through from its input to its output. When
the enable control line is at logic level “1”, the gate output is disabled and a high impedance
condition, Hi-Z, is present on the output.

2.2.2 Tri-state Gate Control
The Tri-state Gate is used in many electronic and microprocessor circuits as they allow multiple
logic devices to be connected to the same wire or bus without damage or loss of data. For example,
suppose we have a data line or data bus with some memory, peripherals, I/O or a CPU connected
to it. Each of these devices is capable of sending or receiving data onto this data bus. If these
devices start to send or receive data at the same time a short circuit may occur when one device
outputs to the bus a logic “1” the supply voltage, while another is set at logic level “0” or ground,
resulting in a short circuit condition and possibly damage to the devices.
Then, the Tri-state Gate can be used to isolate devices and circuits from the data bus and one
another. If the outputs of several Tri-state Buffers are electrically connected together Decoders
are used to allow only one Tri-state Buffer to be active at any one time while the other devices
are in their high impedance state. An example of Tri-state Gates connected to a single wire or
bus is shown in Figure 2.28.

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