Page 32 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 2: Logic Gates

2. The NAND gate output will be low if the two inputs are ...................... . Notes
(a) 00 (b) 01
(c) 10 (d) 11

3. The gates required to build a half adder are ..................... .
(a) EX-OR gate and NOR gate (b) EX-OR gate and OR gate
(c) EX-OR gate and AND gate (d) Four NAND gates.
4. How many AND gates are required to realize Y = CD+EF+G ?

(a) 4 (b) 5
(c) 3 (d) 2
5. When an input signals A=11001 is applied to a NOT gate serially, its output signal
is..................... .
(a) 00111 (b) 00110
(c) 10101 (d) 11001
6. How many two-input AND gates and two-input OR gates are required to realize
Y = BD+CE+AB
(a) 1, 1 (b) 4, 2
(c) 3, 2 (d) 2, 3

7. Which of the following are known as universal gates ..................... .
(a) NAND & NOR (b) AND & OR
(c) XOR & OR (d) None

2.1.6 XOR Gate

XOR stands for exclusive OR. XOR gate compares two values and if they are different its output
will be “1.” XOR operation is represented by the symbol ⊕. So Y = A ⊕ B. You can see XOR logic
gate symbol in Figure 2.6 and its truth table right below it.
Figure 2.17: XOR Logic Gate

Table 2.6: Truth Table

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

So its output will only be at “0” when all its inputs have the same value. Otherwise its output
will be “1.”
If you need more than two inputs, you will need to add an OR gate like shown in Figure 2.18.

LOVELY PROFESSIONAL UNIVERSITY 27