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Digital Circuits and Logic Design



                   Notes
                                 the outputs to be set to y1y0 = 01 only if both w3 and w2 are 0. Input w0 produces the outputs
                                 y1y0 = 00 only if w0 is the only input that is asserted. Alogic circuit that implements the truth
                                 table can be synthesized by using the techniques developed. However, a more convenient way
                                 to derive the circuit is to define a set of intermediate signals, i0, . . . , i3, based on the observations
                                 above. Each signal, ik , is equal to 1 only if the input with the same index, wk , represents the
                                 highest-priority input that is set to 1. The logic expressions for i0, . . . , i3 are

                                                                  i   =  ww ww
                                                                  0    3  2  1  0
                                                                  i   =  ww w 1
                                                                       3
                                                                          2
                                                                  1
                                                                  i   =  ww
                                                                  2    3  2
                                                                  i   =  w 3
                                                                  3
                                 Using the intermediate signals, the rest of the circuit for the priority encoder has the same structure
                                 as the binary encoder in Figure 5.6, namely
                                                                 y   =  i  + i
                                                                  0   1  3
                                                                 y   =  i  + i 3
                                                                      2
                                                                  1
                                 The output z is given by
                                                                  z  =  i  + i + i  + i 3
                                                                            2
                                                                      0
                                                                         1
                                                A simple CPU with 8 registers may use 3-to-8 logic decoders inside the
                                                instruction decoder to select two source registers of the register file to feed into
                                                the ALU as well as the destination register to accept the output of the ALU.


                                             Prepare a truth table of 16-to-4 binary decoder.


                                 5.4 Decoder

                                 Decoder circuits are used to decode encoded information. A binary decoder, depicted in Figure
                                 5.8, is a logic circuit with n inputs and 2  outputs. Only one output is asserted at a time, and each
                                                                n
                                 output corresponds to one valuation of the inputs. The decoder also has an enable input, En, that
                                 is used to disable the outputs; if En = 0, then none of the decoder outputs is asserted. If En = 1,
                                 the valuation of w   •   •  w w  determines which of the outputs is asserted. An n-bit binary code in
                                                       0
                                                     1
                                                n−1
                                 which exactly one of the bits is set to 1 at a time is referred to as one-hot encoded, meaning that
                                 the single bit that is set to 1 is deemed to be “hot.”
                                                        Figure 5.8: An n-to-2n Binary Decoder













                                 The outputs of a binary decoder are one-hot encoded. A 2-to-4 decoder is given in Figure 5.9.
                                 The two data inputs are w1 and w0. They represent a two-bit number that causes the decoder to





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