Page 122 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Introduction to Microprocessors

Notes 2. Treat them separately from memory:

• I/O devices are assigned a “port number” within the 8-bit address range of 00H to FFH.
• The user in this case would access these devices using the IN and OUT instructions only.
• This is called I/O-mapped I/O or Peripheral-mapped I/O.

The first step in interfacing an I/O device would be to determine which instructions will be used
to access it. If you want the user to use the IN/OUT instructions, then it should be interfaced as
a peripheral-mapped I/O device. If the user should use regular data transfer instructions (LDA,
STA, etc.) then it should be interfaced as a memory-mapped I/O device.

8.3.2 Peripheral I/O Instructions

There are two instructions:
• IN brings data (8-bits) from an input device to the accumulator.
• OUT brings data (8-bits) from the accumulator to an output device.

They are both 2 byte instructions with the second byte holding the 8-bit address of the device.
There are separate instructions for input and output, the 8085 can actually
communicate with 256 different input devices AND an additional 256 different
output devices.

8.3.3 The Execution of the OUT Instruction
The OUT instruction requires 3 machine cycles and 10 T-states.

• The first cycle is an opcode fetch cycle to fetch the 1st byte of the instruction from memory
(OUT).

• The second cycle is a memory read cycle to bring the 8-bit port number from the next location.
• The third cycle is an I/O write cycle. In this cycle, the 8085 places the port number on AD0-
AD7 AND A8-A15 and the signal WR is set low (active).

Since the device address is placed on both AD0-AD7 as well as A8-A15, there is no need for de-
multiplexing AD0-AD7. A8-A15 can be used directly to identify the device.

8.3.4 The Execution of the IN Instruction

The execution of the IN instruction is almost identical to that of the OUT instruction. 3 machine
cycles, 10 T-states.
• The first machine cycle is the opcode fetch.

• The second cycle is the memory read to get the port number.
• The third is an I/O Read cycle.
Again, in T1 the port address (8-bits) is placed on both AD0-AD7, and A8-A15. The IO/M signal
is set high to indicate an I/O operation. At the beginning of T2, the RD signal is set low (active)
and the I/O device responds by placing the 8-bit data on the data bus.

8.3.5 The Interfacing of Output Devices
Output devices are usually slow. Also, the output is usually expected to continue appearing on
the output device for a long period of time. Given that the data will only be present on the data
lines for a very short period (microseconds), it has to be latched externally.

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