Page 126 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Introduction to Microprocessors

Notes 8.3.14 Interfacing the Switches (The Program)

• Finally, the program:
IN 0FH ;input data from port 0F into A
HLT ;END
• If we combine both circuits, then we can write the following program:
INPUT: IN 0FH
OUT FFH
JMP INPUT

8.4 Memory Mapped I/O

A peripheral device that assigns specific memory location to inputs and outputs. For example, in
a memory mapped display, each pixel or text character derives its data from a specific memory
byte or bytes. The instant this memory is updated by software, the screen is displaying the new
data.

Memory-mapped I/O (MMIO) and port I/O (also called isolated I/O or port-mapped I/O
abbreviated PMIO) are two complementary methods of performing input/output between the
CPU and peripheral devices in a computer. An alternative approach, not discussed here, is using
dedicated I/O processors commonly known as channels on mainframe computers that execute
their own instructions.

Memory-mapped I/O (not to be confused with memory-mapped file I/O) uses the same address
bus to address both memory and I/O devices - the memory and registers of the I/O devices are
mapped to (associated with) address values. So when an address is used by the CPU it may refer
to a portion of physical RAM, or it can instead refer to memory of the I/O device. Thus, the CPU
instructions used to access the memory are also used for accessing devices. Each I/O device
monitors the CPU’s address bus and responds to any of the CPU’s access of address space assigned
to that device, connecting the data bus to a desirable device’s hardware register. To accommodate
the I/O devices, areas of the addresses used by the CPU must be reserved for I/O and not be
available for normal physical memory. The reservation might be temporary the Commodore 64
could bank switch between its I/O devices and regular memory or permanent.
Port-mapped I/O uses a special class of CPU instructions specifically for performing I/O. This is
generally found on Intel microprocessors, specifically the IN and OUT instructions which can
read and write one to four bytes (outb, outw, outl) to an I/O device. I/O devices have a separate
address space from general memory, either accomplished by an extra “I/O” pin on the CPU’s
physical interface, or an entire bus dedicated to I/O. Because the address space for I/O is isolated
from that for main memory, this is sometimes referred to as isolated I/O.

A device’s direct memory access (DMA) is not affected by those CPU-to-device communication
methods, especially it is not affected by memory mapping. This is because by definition, DMA is
a memory-to-device communication method that bypasses the CPU.
Hardware interrupt is yet another communication method between CPU and peripheral devices.
However, it is always treated separately for a number of reasons. It is device-initiated, as opposed
to the methods mentioned above, which are CPU-initiated. It is also unidirectional, as information
flows only from device to CPU. Lastly, each interrupt line carries only one bit of information
with a fixed meaning, namely “an event that requires attention has occurred in a device on this
interrupt line”.

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