Page 166 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Introduction to Microprocessors

Notes 11.5.2 Nested Loops for Delay

• Instead (or in conjunction with) Register Pairs, a nested loop structure can be used to increase
the total delay produced.
MVI B, 10H 7 T-States
LOOP2 MVI C, FFH 7 T-States

LOOP1 DCR C 4 T-States
JNZ LOOP1 10 T-States
DCR B 4 T-States

JNZ LOOP2 10 T-States

11.5.3 Delay Calculation of Nested Loops
• The calculation remains the same except that it the formula must be applied recursively to
each loop.
– Start with the inner loop, then plug that delay in the calculation of the outer loop.
• Delay of inner loop

–T = 7 T-States
O1
• MVI C, FFH instruction

–T = (255 X 14) - 3 = 3567 T-States
L1
• 14 T-States for the DCR C and JNZ instructions repeated 255 times (FF = 255 ) minus 3 for
16 10
the final JNZ.
–T = 7 + 3567 = 3574 T-States
LOOP1
• Delay of outer loop
–T = 7 T-States
O2
• MVI B, 10H instruction

–T = (16 X (14 + 3574)) - 3 = 57405 T-States
L1
• 14 T-States for the DCR B and JNZ instructions and 3574
T-States for loop1 repeated 16 times (10 = 16 ) minus 3 for the final JNZ.
16 10
–T = 7 + 57405 = 57412 T-States
Delay
• Total Delay

– T = 57412 X 0.5 mSec = 28.706 mSec
Delay

Search more about the looping counter.

11.5.4 Increasing the Delay
The delay can be further increased by using register pairs for each of the loop counters in the
nested loops setup.
It can also be increased by adding dummy instructions (like NOP) in the body of the loop.

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