Page 164 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Introduction to Microprocessors

Notes Useful Instructions: NOP: No operation is performed. The instruction is fetched and decoded;
however, no operation is executed. The instruction is used to fill in time delays and insert
instructions while troubleshooting.

Example:

T-states

MVI C, 0FFh 7
Loop: DCR C 5
JNZ loop 10
In this example, register C is loaded with the count ff (255) by the instruction MVI, which is
executed once and takes seven T-states. The next two instructions, DCR and JNZ, from a loop
with a total of fifteen (5+10) T-states. The loop is repeated 255 times until C=0. The time delay in
the loop TL with 2 MHZ clock frequency is calculated as:-
TL = (T* loop T-states * N10)
Where TL : Time delay in the loop

T: system clock period
N10: equivalent decimal number of the hexadecimal count loaded in the delay register.
= (0.5*10-6 *15*255)
= 1912.5µs
However, to calculate the time delay more accurately, the time for the execution of the initial
instruction MVI should be included in the total time delay TD as:
Delay TD = Time to execute instructions outside loop + time to execute loop instructions
= T0+ TL

= (7*0.5µs)+1912.5µs
= 1916µs
INX rp and DCX rp instruction do not modify the Z flag. In other words, a JZ
or JNZ instruction immediately following a DCX rp or INX rp instruction is
not satisfactory, and an arithmetic or logic operation must be executed first

11.5 Using a Register Pair as a Loop Counter

• Using a single register, one can repeat a loop for a maximum count of 255 times.
• It is possible to increase this count by using a register pair for the loop counter instead of the
single register.

– A minor problem arises in how to test for the final count since DCX and INX do not modify
the flags.

• The following is an example of a delay loop set up with a register pair as the loop counter.
LXI B, 1000H 10 T-States

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