Page 165 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Unit 11: Counters and Time Delays

LOOP DCX B 6 T-States Notes

MOV A, C 4 T-States
ORA B 4 T-States
JNZ LOOP 10 T-States

• Using the same formula from before, we can calculate:
• T = 10 T-States
O
– The delay for the LXI instruction
• T = (24 X 4096) - 3 = 98301 T- States
L
– 24 T-States for the 4 instructions in the loop repeated 4096 times (1000 = 4096 ) reduced
16 10
by the 3 T-States for the JNZ in the last iteration.
• T = (10 + 98301) X 0.5 mSec = 49.155 mSec
Delay
If the loop is looking for when the count becomes zero, we can use a small trick by
ORing the two registers in the pair and then checking the zero flag.

11.5.1 Nested Loops

• Nested loops can be easily setup in Assembly language by using two registers for the two
loop counters and updating the right register in the right loop.

– In the Figure, the body of loop2 can be before or after loop1.

Figure 11.8: Nested Loops

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