Page 21 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Unit 1: Microprocessors and Microcomputers

instruction specifies the address of the desired subroutine; the register indirect address is the Notes
stack pointer. The CALL instruction pushes the current contents of the program counter into the
memory location specified by the stack pointer.
1.4.7 Timing Effects of Addressing Modes

Addressing modes affect both the amount of time required for executing an instruction and the
amount of memory required for its storage. For example, instructions that use implied or register
addressing, execute very quickly since they deal directly with the processor’s hardware or with
data already present in hardware registers. Most important, however, is that the entire instruction
can be fetched with a single memory access. The number of memory accesses required is the
single greatest factor in determining execution timing. More memory accesses therefore require
more execution time. A CALL instruction, for example, requires five memory accesses: three to
access the entire instruction and two more to push the contents of the program counter onto the
stack.

The processor can access memory once during each processor cycle. Each cycle comprises a variable
number of states. The length of a state depends on the clock frequency specified for your system,
and may range from 480 nanoseconds to 2 microseconds. Thus, the timing for a four-state
instruction may range from 1.920 microseconds through 8 microseconds. (The 8085 have a
maximum clock frequency of 5 MHz and therefore a minimum state length of 200 nanoseconds.)

Create the set of assembly language instruction for the simple microprocessor.

1.4.8 Decoding
The instruction decoder needs to turn each of the opcodes into a set of signals that drive the
different components inside the microprocessor. Let’s take the ADD instruction as an example
and look at what it needs to do:

1. During the first clock cycle, we need to actually load the instruction. Therefore the instruction
decoder needs to:
• activate the tri-state buffer for the program counter

• activate the RD line
• activate the data-in tri-state buffer
• latch the instruction into the instruction register

2. During the second clock cycle, the ADD instruction is decoded. It needs to do very little:
• set the operation of the ALU to addition
• latch the output of the ALU into the C register

3. During the third clock cycle, the program counter is incremented (in theory this could be
overlapped into the second clock cycle).
Every instruction can be broken down as a set of sequenced operations like these that manipulate
the components of the microprocessor in the proper order. Some instructions, like this ADD
instruction, might take two or three clock cycles. Others might take five or six clock cycles.

The mnemonics assigned to the instructions are designed to indicate the function
of the instruction.

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