Page 142 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 8: Memory

The vertical wires are called the AND plane. We often leave out the AND gates to make it even Notes
easier to draw.
We then add OR gates using horizontal wires, to connect the minterms together.
Figure 8.9: Horizontal Wires

Again, a single wire into the OR gate is really 4 wires. We use the same simplification to make
it easier to read.

The horizontal wires make up the OR plane.
This is how the PLA looks when we leave out the AND gates and the OR gates. It is not that the
AND gates and OR gates are not there–they are, but they have been left out to make the PLA
even easier to draw.
Figure 8.10: PLA without AND and OR Gates

8.6.1 Minterms

Given n variables, it would seem necessary to have 2 vertical wires (for the AND gates), one for
n
each possible minterm. However, 2 grows very quickly. So, sometimes there are not 2 vertical
n
n
wires.
You can generally get around the problem by not connecting the wire to each of the three variables.
For example, you could just have a product term x \x or even simply \x .
2 0 1
For the purpose of implementing truth tables, we will usually tell you not to simplify, and to let
each vertical line be a minterm.
8.6.2 Programming

What does it mean to program a PLA? See the black dots. Those connections are made between
wires. In effect “programming” the wires means to make the connections within the PLA.
Configurable might be a better word than programmable, but that is the name that stuck.

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