Page 145 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design

Notes 8.7 Programmable Array Logic (PAL)

A ROM has a large number of fusible links (m × 2 ) because of the large number (2 ) of AND
n
n
gates. Programming of links is performed only on the outputs from the AND gates. In a PLA, the
number of links is drastically reduced by reducing the number of AND gates. The latter is done
by changing the expression representing the switching function from a canonic sum-of-products
form to a sum of products with fewer terms. The price paid is the need to program not only the
outputs from the AND gates, but also the inputs to the AND gates. What other possibility for
programming is there beyond the two cases of (a) programming the outputs of the AND gates
and (b) programming both the inputs and the outputs? We are sure you answered, “Programming
only the inputs.” This is a possibility, but is it worthwhile?
In the case of the ROM, there is no need to program the inputs because, for any function of n
variables, there will be the same (large) number of AND gates. In the same way, if the number
of OR gates at the output could be fixed, then programming the outputs of the AND gates could
be avoided.
In many circuits with multiple outputs, even though the outputs are functions of a large number
of input variables, the number of product terms in each output is small. Hence, the number of
AND gates that drive each OR gate is small. In such cases, permanently fixing the number of OR
gates and leaving only the programming of the AND gate inputs for individual design might
make economic sense. The resulting circuit is called programmed array logic (PAL). The number
of fusible links in a PAL is only 2np. Standard PALs for a number of low values of p exist. For
example, the PAL16L8 has a maximum of 16 inputs and 8 outputs.

A programming table for a PAL is similar to the one for a PLA. A case with six outputs is illustrated
in Figure 8.12. A ROM with 12 input variables would require 2 = 4096 AND gates. However, let
12
us assume that for some possible cases, the canonic sum-of-products expression can be reduced to
16 applicants, only one of which is shown in Figure 8.12. The entries in the table would have the
same meanings as those for the PLA. However, for the PAL, the output columns would be fixed
by the manufacturer on the basis of the number of AND gates already connected to each OR gate.

Figure 8.12: Programming Table for a PAL Example

In the present case, two of the output OR gates are each driven by four AND gates; the remaining
four OR gates are each driven by two AND gates. For any given design problem, the first step is to
obtain an appropriate sum-of-products expression, just as in the case of a PLA implementation. The
input connections are indicated in the table as in the case of the PAL: an entry is an 1 if a variable
appears un-complemented in an implicit, a 0 if it appears complemented, and a dash if it does
not appear at all. This is illustrated for one row in Figure 8.12. The number of fusible links in this
example is 2 × 12 × 16 = 384. This is 20 percent fewer than the number of links of a PLA having

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