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Unit 10: Clocked Sequential Circuits



            10.2 Analysis of Clocked Sequential Circuits                                          Notes

            Analysis of clocked sequential circuits with an example
                                Figure 10.4: Sequential Circuit Design Steps



                             Verbal
                          Description of
                           the Problem                         Circuit
                                                              Diagram



                                           State Diagram



                                                               FF I/P
                                                             Equations &
                           State Table                          Q/P
                                                             Equations
                                                                        Excitation

                                Minimization
                                                                        Flip-Flop
                                 Techniques                               Tables


                                                State        Output and
                            Reduced           Assignment       States
                           State Table                       Transition
                                                               Table


            The behaviour of a sequential circuit is determined from the inputs, outputs and states of its
            flip-flops.
            Both the outputs and the next state are a function of the inputs and the present state.

            Recall from previous lesson that sequential circuit design involves the flow as shown.
            Analysis consists of obtaining a state-table or a state-diagram from a given sequential circuit
            implementation. In other words analysis closes the loop by forming state-table from a given
            circuit-implementation. We will show the analysis procedure by deriving the state table of the
            example circuit we considered in synthesis. The circuit is shown in Figure 10.5.
                                 Figure 10.5: A Clocked Sequential Circuit
























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