Page 170 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 10: Clocked Sequential Circuits

The analysis can start from any arbitrary state. Let us start deriving the state table from the initial Notes
state 00. As a first step, the input equations to the flip-flops and to the combinational circuit must
be obtained from the given logic diagram. These equations are:
J = BX’
A
K = BX + B’X’
A
D = X
B
y = ABX
The first row of the state-table is obtained as follows:
When input X = 0; and present states A = 0 and B = 0 (as in the first row);
then, using the above equations we get:
y = 0, J = 0, K = 1, and D = 0.
B
A
A
The resulting state table is exactly same from which we started our design example. Thus, analysis
is opposite to design and combined, and they act as a closed loop.
A clocked sequential system is a kind of Moore machine, and a Moore machine
is a finite-state machine whose output values are determined solely by its
current state.

Draw a synchronous sequential logic circuit diagram.

Self Assessment

Multiple choice questions:
1. Sequential circuits have a clock signal as one of their .................. .
( a) next-state (b) inputs
( c) clock (d) outputs

2. The behaviour of a sequential circuit is determined from the ................ .
( a) inputs (b) outputs
( c) flip-flops (d) all of these
3. A state table is representation of sequence of ....................... states in a tabular form.
( a) inputs (b) outputs
( c) flip-flops (d) All of these.
4. The number of rows in the state table is equal to...................... .
( a) 2 (number of flip-flops + number of inputs)
( b) 2 (number of flip-flops - number of inputs)
( c) 2 (number of flip-flops*number of inputs)
( d) 2 (number of flip-flops/number of inputs)
5. The problem of ....................... is to find ways of reducing the number of states in a sequential
circuit without altering the input-output relationships.

(a) unused states (b) states assignment
( c) state reduction (d) states hazard

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