Page 165 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design Avinash Bhagat, Lovely Professional University

Notes Unit 10: Clocked Sequential Circuits

CONTENTS
Objectives
Introduction
10.1 Sequential Circuits
10.2 Analysis of Clocked Sequential Circuits
10.2.1 State Reduction
10.2.2 States Assignment
10.2.3 Design with Unused States
10.2.4 Unused States Hazard
10.3 Clocked Sequential Circuits Design
10.3.1 State Diagram
10.3.2 State Table
10.3.3 K-map
10.3.4 Circuit
10.4 State Minimization
10.4.1 State Equivalence
10.4.2 Partitioning Minimization
10.5 State Assignment
10.5.1 State Maps
10.5.2 Minimum-Bit-Change Strategy
10.5.3 Prioritized Adjacency Strategy
10.6 Summary
10.7 Keywords
10.8 Review Questions
10.9 Further Reading

Objectives

After studying this unit, you will be able to:
• Explain the sequential circuits
• Discuss about the analysis of clocked sequential circuits
• Explain the sequential circuits design
• Explain the state minimization
• Explain the state assignment

Introduction

In digital electronics, a clocked sequential system is a system whose output depends only on the
current state, whose state changes only when a global clock signal changes, and whose next-state
depends only on the current state and the inputs.

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