Page 160 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 9: Flip-Flops

A timing signal generating circuit including a clock source which generates clock pulses of a Notes
predetermined period, a binary counter which divides the frequency of the clock pulses from
the clock source by n, a logical array which decodes an output of the binary counter and which
is composed of semiconductor elements and flip-flop circuits which are set or reset by outputs
of the logical array in response to the clock pulses from the clock source with the outputs of the
flip-flop circuits being used as timing signals.
Timing analysis of all signals must be performed. In general, the signals fall into two classes.
First, signals such as data, enables, and synchronous inputs must meet set-up (t ) and hold (t )
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times. Clock signals must meet width (t ) requirements. These are well-defined and commonly
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used and will not be discussed further in this application note.
A common mistake in the analysis of digital systems is the timing analysis of asynchronous
signals. With respect to flip-flops, these inputs are usually called PRESET and CLEAR. For MSI
devices, there are other signals that are similar such as the JAM input to counters or shift registers.
Although these signals are labeled “asynchronous” they do have restrictions on their use. Failure
to meet the specifications can result in incorrect operation.

The first specification that these signals must meet is minimum pulse width. This is rather
straightforward. If this specification is not met, the signal may be ignored or the flip-flop may be
driven into a meta stable state.
A more subtle requirement, and the one that is commonly missed, is the removal time which is
often referred to as tREM. Note that not all manufacturers use this nomenclature; there may be
different terms. Essentially, this is the equivalent of a set up time requirement for synchronous
inputs. That is, the asynchronous command must be removed at least tREM prior to the next
active edge of the clock. As in the case above, if this specification is not met, the signal may be
ignored or the flip-flop may be driven into a meta stable state.

Lastly, for MSI devices or modules that emulate them, data that is “jammed,” as well as any related
mode or address inputs, must meet set up and hold times with respect to the asynchronous pulse,
similar to that of synchronous signals to the clock.
Some timing signals requirements of asynchronous inputs of flip-flops are similar to those of
clocks; others to those of synchronous data. Specifically, the timing analysis of asynchronous
signals must show:
1. Proper pulse width of the asynchronous pulse.
2. Removal of the asynchronous command pulse tREM prior to the next active edge of the
clock. This is the equivalent to a setup time requirement.
3. Proper asynchronous data set-up and hold times with respect to the pulse.

Note that all manufacturers list in their device specification is not the tREM parameters (or its
equivalent). However, all flip-flops do have this requirement; unfortunately not all data sheets
specify it. The asynchronous inputs may not be removed asynchronously to the clock for reliable
operation.

Flip-Flop was the first time an electronic circuit which had stored a “piece of
information”.

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