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Digital Circuits and Logic Design



                   Notes         the negative transition of the clock pulse. Some master-slave flip-flops change output state on the
                                 positive transition of the clock pulse by having an additional inverter between the CP terminal
                                 and the input of the master.

                                               Figure 9.8: Timing Relationship in a Master Slave Flip-Flop














                                 9.4 Triggering of Flip-Flop

                                 The state of a flip-flop is changed by a momentary change in the input signal. This change is called a
                                 trigger and the transition it causes is said to trigger the flip-flop. The basic circuits of Figure 9.1 and
                                 Figure 9.2 require an input trigger defined by a change in signal level. This level must be returned
                                 to its initial level before a second trigger is applied. Clocked flip-flops are triggered by pulses.
                                 The feedback path between the combinational circuit and memory elements in Figure 9.9 can
                                 produce instability if the outputs of the memory elements (flip-flops) are changing while the
                                 outputs of the combinational circuit that go to the flip-flop inputs are being sampled by the clock
                                 pulse. A way to solve the feedback timing problem is to make the flip-flop sensitive to the pulse
                                 transition rather than the pulse duration.
                                 The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1 to 0.
                                 As shown in Figure 9.9 the positive transition is defined as the positive edge and the negative
                                 transition as the negative edge.
                                                    Figure 9.9: Definition of Clock Pulse Transition











                                 The clocked flip-flops already introduced are triggered during the positive edge of the pulse, and
                                 the state transition starts as soon as the pulse reaches the logic-1 level. If the other inputs change
                                 while the clock is still 1, a new output state may occur. If the flip-flop is made to respond to the
                                 positive (or negative) edge transition only, instead of the entire pulse duration, then the multiple-
                                 transition problem can be eliminated.
                                 9.5 Timing Signal


                                 (Computer science) A pulse generated by the clock of a digital computer to provide synchronization
                                 of its activities.
                                 (Electronics) Any signal recorded simultaneously with data on magnetic tape for use in identifying
                                 the exact time of each recorded event.




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