Page 158 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 9: Flip-Flops

Self Assessment Notes

Multiple choice questions:
1. The NAND gate output will be low if the two inputs are

(a) 00 (b) 01
(c) 10 (d) 11
2. A ring counter consisting of five Flip-Flops will have

(a) 5 states (b) 10 states
(c) 32 states (d) Infinite states
3. If the input to T Flip-Flop is 100 Hz signal, the final output of the three T Flip-Flops in cascade
is:
(a) 1000 Hz (b) 500 Hz

(c) 333 Hz (d) 12.5 Hz
4. In a JK Flip-Flop, toggle means:
(a) Set Q = 1 and Q = 0

(b) Set Q = 0 and Q = 1
(c) Change the output to the opposite state

(d) No change in output
5. A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The
maximum possible time required for change of state will be:
(a) 15 ns (b) 30 ns
(c) 45 ns (d) 60 ns

9.3 Master-Slave Flip-Flop

A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a master
and the other as a slave. The logic diagram of an SR flip-flop is shown in Figure 9.7. The master
flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is disabled by
the inverter. The information at the external R and S inputs is transmitted to the master flip-flop.
When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled. The
slave flip-flop then goes to the same state as the master flip-flop.

Figure 9.7: Logic Diagram of a Master-Slave Flip-Flop

The timing relationship is shown in Figure 9.8 and is assumed that the flip-flop is in the clear state
prior to the occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on

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