Page 156 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 9: Flip-Flops

A clocked JK flip-flop is shown in Figure 9.4. Output Q is ANDed with K and CP inputs so that the Notes
flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q’ is ANDed
with J and CP inputs so that the flip-flop is set with a clock pulse only if Q’ was previously 1.
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1
(while J=K=1) after the outputs have been complemented once will cause repeated and continuous
transitions of the outputs. To avoid this, the clock pulses must have time duration less than the
propagation delay through the flip-flop. The restriction on the pulse width can be eliminated
with a master-slave or edge-triggered construction. The same reasoning also applies to the T
flip-flop presented next.

Figure 9.4: Clocked JK Flip-Flop (a) Logic Diagram
(b) Graphical Symbol (c) Transition Table

K
Q
CP

Q
J

a
()

J Q
CP
K Q

()
b
Q JK Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
()
c

Create a structure to make the Q output of JK flip-flop always changes upon the
occurrence of the active transition?

9.2.3 T Flip-Flop

The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 9.5, the T flip-flop is
obtained from the JK type if both inputs are tied together. The output of the T flip-flop “toggles”
with each clock pulse.

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