Page 162 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 9: Flip-Flops

Self Assessment Notes
Multiple choice questions:
6. How many Flip-Flops are required to construct a decade counter
(a) 10 (b) 3
(c) 4 (d) 2
7. How many Flip-Flops are required to construct mod-30 counter
(a) 5 (b) 6
(c) 4 (d) 8
8. For JK Flip-Flop with J = 1, K = 0, the output after clock pulse will be
(a) 0 (b) 1
(c) high impedance (d) no change

9. The output of SR Flip-Flop when S = 1, R = 0 is
(a) 1 (b) 0
(c) No change (d) High impedance

9.6 Summary

• A flip-flop circuit constructed from either two NAND gates or two NOR gates.
• State of a flip-flop is changed by a momentary change in the input signal. This change is
called a trigger and the transition it causes is said to trigger the flip-flop.
• Master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a
master and the other as a slave.

• The state of a flip-flop is changed by a momentary change in the input signal.
• A timing signal generating circuit including a clock source which generates clock pulses of
a predetermined period, a binary counter which divides the frequency of the clock pulses
from the clock source by n, a logical array which decodes an output of the binary counter.
• Timing analysis of all signals must be performed.

9.7 Keywords

Clocked flip-flops: This is introduced triggered during the positive edge of the pulse, and the
state transition starts as soon as the pulse reaches the logic-1 level.
D flip-flop: It is a modification of the clocked SR flip-flop the D input goes directly into the S input
and the complement of the D input goes to the R input.
Flip-flops: It is not the sandals, but the logic gates, are the fundamental building blocks of
sequential logic.

JK flip-flop: It is a refinement of the SR flip-flop in that the indeterminate state of the SR type is
defined in the JK type.

Master-slave flip-flop: It occurs on the negative transition of the clock pulse some master-slave
flip-flops change output state on the positive transition of the clock pulse by having an additional
inverter between the CP terminal and the input of the master.
SR flip-flop: It consists of a basic NOR flip-flop and two AND, gates the outputs of the two AND
gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input values.

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