Page 192 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 11: Registers and Counters

Notes
1 0 0 0
3nd data bit =1 D D D D Q 3
C C C C
After CLK2
CLK2

0 1 0 0
3rd data bit =0 D D D D Q 1
C C C C
After CLK3

CLK3
1 0 1 0
4th data bit =1 D D D D Q 3
C C C C After CLK-4, the 4-bit
member is completely
stored in register.
CLK4
Figure 11.5: Four Bits (1010) Being Serially Shifted Out of the
Register and Replaced by All Zeros

FF0 FF1 FF2 FF3
1 0 1 0
0 D D D D 1st data bit
Q 3
C C C C
After CLK-4, register
contains into
CLK

0 1 0 1
0 D D D D 2nd data bit
Q
3
C C C C
After CLK5
CLK5

0 0 1 0
0 D D D D 3rd data bit
Q 3
C C C C
After CLK6

CLK6

0 0 0 0
0 D D D D 4th data bit
Q
3
C C C C
After CLK7

CLK7
0 0 0 0
0 D D D D
Q 3
C C C C
After CLK8, register
is CLEAR
CLK8

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