Page 195 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS
P. 195
Digital Circuits and Logic Design
Notes
Figure 11.9: The Timing Diagram of 74HC164
CLR
A
Serial
Inputs
B
CLK
Q 0
Q 1
Q 2
Q 3
Outputs
Q 4
Q 5
Q 6
Q 7
Take care while using common bus lines not to allow more than one device to
be enabled at a time. System noise and incorrect data problems could result,
and depending on output drive capability, physical damage to the device
could occur.
11.1.3 Parallel-In/Serial-Out Shift Registers
A four-bit parallel-in/serial-out shift register is shown below. The circuit uses D flip-flops and
NAND gates for entering data, (i.e. writing) to the register.
Figure 11.10: Four-Bit Parallel-in/Serial-out Shift Register
D0 D1 D2 D3
WRITE/
SHIFT
D SET Q D SET Q D SET Q D SET Q
CLK Output
data
CLR Q CLR Q CLR Q CLR Q
CLEAR
D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least
significant bit. To write data in, the mode control line is taken to LOW and the data is clocked in.
The data can be shifted when the mode control line is HIGH as SHIFT is active high. The register
performs right shift operation on the application of a clock pulse, as shown in the table 11.4.
190 LOVELY PROFESSIONAL UNIVERSITY
