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Unit 11: Registers and Counters
In the diagram above, the J, K and CLK inputs are wired the same way as a synchronous up Notes
counter. The asynchronous PRESET and CLEAR inputs are used to perform the asynchronous
presetting. The counter is loaded by applying the desired binary number to the inputs P , P and
2 1
P and a LOW pulse is applied to the PARALLEL LOAD input, not (PL). This will asynchronously
0
transfer P , P and P into the flip-flops. This transfer occurs independently of the J, K, and CLK
2 1 0
inputs. As long as not(PL) remains in the LOW state, the CLK input has no effect on the flip-flop.
After not(PL) returns to high, the counter resumes counting, starting from the number that was
loaded into the counter.
For the example above, say that P = 1, P = 0, and P = 1. When not (PL) is high, these inputs have
2 1 0
no effect. The counter will perform normal count-up operations if there are clock pulses. Now,
let us say that not (PL) goes low at Q = 0, Q = 1 and Q = 0. This will produce LOW states at the
2 1 0
CLEAR input of Q , and the PRESET inputs of Q and Q . This will make the counter go to state
1
2
0
101 regardless of what is occurring at the CLK input. The counter will remain at state 101 until
not (PL) goes back to HIGH. The counter will then continue counting from 101.
11.4 Memory Decoding
The need for memory address decoding arises from the fact that the main memory of a computer
system is not constructed from a single component, which uniquely addresses each possible
memory location.
Imagine a situation where two 1M memory chips are connected to a 32-bit address bus to make 2M
of memory available. Each memory chip will need twenty address lines to uniquely identify each
location in it. If the address lines of each memory chip were simply connected to the first twenty
CPU address lines, then both memory chips would be accessed simultaneously whenever the CPU
referred to any address. There are several memory addressing schemes that address this problem.
11.4.1 Partial Address Decoding
This is the simplest and least expensive form of address decoding. In the above example, we could
connect the chip select input of one memory chip to the last CPU address line, and the chip select
input of the other to the same address line but via an inverter. In this way the two chips would
never be accessed simultaneously.
However, this is very inefficient. Eleven of the address lines are not used, and one of the two
memory chips is always selected. The usable address space of the computer has been reduced
from 4G to 2K. Partial address decoding is used in small dedicated systems where low cost is the
most important factor. The penalty paid is that not all the address space can be used, and future
expansion will be difficult.
11.4.2 Full Address Decoding
Full address decoding is when each addressable location within a memory component corresponds
to a single address on the CPU’s address bus. That is, every address line is used to specify each
physical memory location, through a combination of specifying a device and a location within it.
Full address decoding is very efficient in the use of the available address space, but is often
impracticable to use because of the excessive hardware needed to implement it. This is particularly
true where devices with a small number of addressable locations (for example memory-mapped
I/O devices) are used.
11.4.3 Block Address Decoding
Block address decoding is the merger of partial address decoding and full address decoding. The
memory space is divided into a number of blocks. For example, in a system with a 32-bit address
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