Page 203 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design

Notes
Figure11.25: 4-bit Synchronous Binary Up Counter
AB
ABC A
B
C
1
D J C J B J A J
CLK CLK CLK CLK
K K K K
1

Input
From the diagram above, we can see that although the counter is synchronous and is supposed
to change simultaneously, we have a propagation delay through the AND gates which add up
to give an overall propagation delay which is proportional to the number of bits of the counter.
To overcome this problem, we can feed the outputs from the flip-flops directly to a many-input
AND gate as follows:
Figure 11.26: 4-bit Synchronous Binary Up Counter Using Speedup Technique

This method does over comes the problem of additive propagation delay but introduces some
other problem of its own. From the diagram above, we can see that the third flip-flop gets its J-K
input from the output of a 2-input AND gate and the fourth flip-flop gets its input from a 3-input
AND gate and so on. If we have a counter that counts to, for example, 16-bits, we will need to have:
1 * 15-input AND gate,
1 * 14-input AND gate,
...
...

1 * 3-input AND gate and
1 * 2-input AND gate.
This method obviously uses a lot more resources than the first method. Not only that, in the first
method, the output from each flip-flop is only used as an input to one AND gate. In the second
method, the output from each flip-flop is used as an input to all the higher-order bits. If we have
a 12-bit counter, the output of the first flip-flop will have to drive 10 gates (called fan-out). The
output from the flip-flop may not have the power to do this.

The “solution” to this is to use a compromise between the two methods. Say we have a 12-bit
counter; we can organize it into 3 groups of 4. Within each group of 4, we use the second method
and between the 3 groups, use the first method. This way, we only have an overall gate propagation
delay and a maximum fan-out of 3 instead of 10 using the first and second method respectively.

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