Page 87 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Unit 6: The 8085 Microprocessor Architecture

ALE (Pin 30) Notes
All memory chips have a memory address register (MAR), also called the address latch. This
stores the address from the address bus and is connected to the memory chip. The falling edge of
the ALE signal loads the address bus into the MAR of the memory chip. ALE stands for address
latch enable and is used to indicate that the information carried on the multiplexed address/data
bus (AD to AD), is the lower order address byte when a logic high condition appears on this line.
0
Hence this control line is used to latch the lower order address A to A from the multiplexed
0
address/data bus in the 1 clock of the machine cycle.
WR (Pin 31)
A low condition i.e., 0 on the WR pin intends to output (write) data on the data bus are to be
written into the selected I/O devices or memory.
RD (Pin 32)
A low condition i.e., 0 on the RD pin indicates that the microprocessor intends to receive (read)
the data from the I/O devices or memory locations and date are available on the data bus.
1O/M (Pin 34)
This pin indicates whether the address on the address bus is meant for the I/O devices or for the
memory locations. A logic high i.e., 1 on this pin indicates that the address on the address bus is
meant for the I/O devices while the logic low i.e., 0 on this pin indicates that the address on the
address bus is meant for the memory locations.

Ready (Pin 35) (Input)
The I/O or memory devices are not as fast as the microprocessor and a mechanism is required to
tell the microprocessor that the data from the I/O devices or from the memory are not readily
available at a particular moment. It indicates the microprocessor to wait up to the time the data
becomes available. When READY = 0, the microprocessor waits till READY = 1 and when READY
= 1, the microprocessor knows that the data is now available from the I/O devices or from the
memory.
Reset In (Pin 36)
When the signal on this pin becomes low for at least 600 nano seconds, it forces the microprocessor
to do the following:
• (PC) = 0
• Instruction register cleared
• All interrupts (except TRAP) disabled
• SOD = 0
• Data, address and control bus are floated
CLK OUT (Pin 37)
The clock signal is derived from the on chip: oscillator and the CLK derive the peripherals to
synchronize their timings. This signal can be used as the system clock for other devices.
Hold (Pin 38) (Output)
In order to speed up the data transfer between memory and a peripheral device, the microprocessor
need not be involved. This is implemented by the DMA (Direct memory address). Hence HOLD
and HLDA control signals are required for the DMA operation. A logic high i.e,1 on this pin
input by any I/O device indicates that the data is ready for DMA transfer.

HLDA (Pin 39) (Input)
This stands for hold acknowledge. A logic high condition on this pin indicates; that the
microprocessor has received the information of request from the 1/O devices and will relinquish
the data, address and control buses after completion of the current bus transfer.

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