Page 92 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Introduction to Microprocessors

Notes 6.2.3 Address Buffer and Address Data Buffer

The contents of the stack pointer or program counter can be loaded into the address buffer and
address-data buffer. The output of these buffers then drives the external address bus and address-
data latches. Memory and I/O chips are also connected to these buses through buffers decoders.
The CPU can thus send the address of the desired data to the memory and I10 chips. The 8-bit
internal data bus is also connected to the address-data buffer. The input to this section is from
incrementer/decrementer section below registers.
6.2.4 Interrupt Controls
To answer a request from an I/O device, it is sometimes necessary to interrupt the execution of
the main program currently being executed. The CPU temporarily stops execution and attends
the I/O device which has interrupted, the CPU, then returns to what it was doing.
The 8085 A has five hardware interrupts: INTR, RST 5.5, RST 6.5, RST 7.5 and TRAP. These can be
classified into three types depending on their maskability. The first of its types is INTR. INTR
(Input) i.e., Interrupt request. This is a general purpose interrupt. INTA (Output) i.e., Interrupt
acknowledge. This is used to acknowledge an interrupt. In the second group is RST 5.5, RST i-5
and RST 7.5. These are input-restart interrupts. These are vector interrupts that transfer the program
control to specific memory locations. They have higher priorities than the INTR interrupt: Among
these three, the priority order is 7.5, 6.5 and 5.5. These are vector interrupt. The TRAP is the third
kind of hardware interrupt.
If two or more interrupt go high at the same time, the CPU will service them in the order of their
priority. TRAP has the highest priority, which is non-maskable. The priority is in Table 6.3:

Table 6.3: Interrupt Priorities

Interrupt Name Priority of Interrupt Call Location

TRAP 1 0024H
RST 7.5 2 003CH

RST 6.5 3 0034H
RST 5.5 4 002CH

INTR 5 —

6.2.5 Serial Input/Output Control
The 8085 CPU works on 8-bit parallel data. Sometimes I/O devices with serial data, when want
to communicate, the serial data stream from an input device must be converted to 8-bit parallel
data before this input enters the 8085 and the CPU can use. Same way the 8-bit data out of CPU
must be converted to serial form before it is fed to a serial output device. The SID input is used
where serial data enters the 8085 and SOD output is used where serial data leaves the 8085 to be
used for the I/O devices which work with the serial data.
The SIM (Set Interrupt Mask) and RIM (Read Interrupt Mask) instruction allows to perform the
conversion needed for serial I/O devices.

SIM is a 1-byte instruction can be used for three different functions:
(a) Set mask for RST 7.5, 6.5 and 5.5 interrupts
(b) Reset RST 7.5 flipflop.
(c) Implement serial I/O.

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