Page 94 - DCAP210_INTRODUCTION__TO_MICROPROCESSORS

Introduction to Microprocessors

Notes (d) Register Indirect Addressing: In this mode of addressing the operands are addressed
through register pairs. It means that the data location is specified by indirect method. The
register pair is having address of memory location from where data is to be accessed. For
example LXI H, 2050H which loads the HL register pair with 2050H and MOVA, M moves
the contents of the memory location whose address is in the HL pair to the Accumulator.
ADD, M is another example of this mode of addressing.
(e) Implicit Addressing: This is the mode of addressing in which the contents data of the
Accumulator are operated upon and does not require the address of the operands. For
example the instructions CMA, RAL, RAR etc. does not require other operands then the
available in the Accumulator.

Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64 KB.

6.2.7 Timing Diagram of 8085
For execution of an instruction, a microprocessor fetches the instruction and executes it. The time
taken for the execution of an instruction is called Instruction Cycle. An instruction cycle consists
of a fetch cycle and executes cycle. The execution of any program consists of READ or WRITE
operations, of which each transfer a byte of data between the CPU and a particular I/O device or
memory.
Each READ or WRITE operation of the CPU is referred to as Machine Cycle. Machine cycle is
defined as the time required to complete one operation of accessing memory, I/O or
acknowledging an external request. An instruction’s execution consists of a number of machine
cycles. These cycles vary from one to five depending on the instruction. Each machine cycle
contains a number of clock cycles which are called states. T-State is defined as one subdivision of
the operation performed in one clock period. The first machine cycle will be executed by either
four or six clock periods or the machine cycles that follow will have three clock periods. The
8085A machine cycle has been shown in Figure 6.8.
Figure 6.8: Machine Cycle of 8085

The shaded clock periods (T and T ) mean that these are needed in M by some of the instructions.
5 6 l
The control and statue signals are shown below:
Machine Status Control

IO/ M S S RD WR INT A
1 0
Opcode Fetch(OF) 0 1 1 0 1 1
Memory Read 0 1 0 0 1 1

Memory write 0 0 1 1 0 1
I/O Read 1 0 0 1 1
I/O Write 0 1 1 0 1

INTR ACK 1 1 1 1 1 0
HALT TRISTATED 0 0 TRISTATE TRISTATE 1

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