Page 105 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design

Notes suitable for driving a digit-oriented display. As illustrated in Figure 6.15a, the circuit converts the
BCD digit into seven signals that are used to drive the segments in the display. Each segment is a
small light-emitting diode (LED), which glows when driven by an electrical signal. The segments
are labelled from a to g in the figure. The truth table for the BCD-to-7-segment decoder is given
in Figure 6.15c. For each valuation of the inputs w ,..............,w , the seven outputs are set to
3 0
Figure 6.15: A BCD-to-7-Segment Display Code Converter (a) Code Converter
(b) 7-segment Display (c) Truth Table

a a
b
w 0 f b
w 1 c d
w g
2 e e c
w
3 f
g d
() ()
b
a
w w w w 0 ab c d ef g
3
1
2
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
() c

display the appropriate BCD digit. Note that the last 6 rows of a complete 16-row truth table are
not shown. They represent don’t-care conditions because they are not legal BCD codes and will
never occur in a circuit that deals with BCD data. Acircuit that implements the truth table can be
derived using the synthesis techniques. Finally, we should note that although the word decoder
is traditionally used for this circuit, a more appropriate term is code converter. The term decoder
is more appropriate for circuits that produce one-hot encoded outputs.
A seven-segment display (SSD), or seven-segment indicator, is a form of
electronic display device for displaying decimal numerals that is an alternative
to the more complex dot-matrix displays.

6.4 Comparators

A comparator is a device that compares two voltages or currents and switches its output to
indicate which is larger.
Another useful type of arithmetic circuit compares the relative sizes of two binary numbers. Such a
circuit is called a comparator. This considers the design of a comparator that has two n-bit inputs,
A and B, which represent unsigned binary numbers. The comparator produces three outputs,
called AeqB, AgtB, and AltB. The AeqB output is set to 1 if A and B are equal. The AgtB output
is 1 if A is greater than B, and the AltB output is 1 if A is less than B. The desired comparator
can be designed by creating a truth table that specifies the three outputs as functions of A and B.
However, even for moderate values of n, the truth table is large. A better approach is to derive
the comparator circuit by considering the bits of A and B in pairs. We can illustrate this by a small

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