Page 127 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design

Notes • The present invention facilitates semiconductor fabrication by employing high-k dielectric
layers in NMOS regions but not in PMOS regions of semiconductor transistor devices.

• NMOS devices within an I/O region having higher operation voltage requirements employ
a high-k dielectric layer and a first oxide layer as dielectric layers. NMOS devices within a
core region of the device employ only the high-k dielectric layer as a dielectric layer. As a
result, high-k dielectric materials are employed for the NMOS devices without negatively
impacting operation of the PMOS devices.
7.7.5 CMOS versus TTL
CMOS

The term ‘Complementary Metal-Oxide-Semiconductor’, or simply ‘CMOS’, refers to the device
technology for designing and fabricating integrated circuits that employ logic using both n- and
p-channel MOSFET’s. CMOS is the other major technology utilized in manufacturing digital
IC’s aside from TTL, and is now widely used in microprocessors, memories, and digital ASIC’s.
TTL

Transistor-Transistor Logic, or TTL, refers to the technology for designing and fabricating digital
integrated circuits that employ logic gates consisting primarily of bipolar transistors. It overcomes
the main problem associated with DTL, i.e. lack of speed.
Comparisons between CMOS and TTL are given below:
• The input to a CMOS circuit is always to the gate of the input MOS transistor, which exhibits
a very high resistance. This high gate resistance is due to the fact that the gate of a MOS
transistor is isolated from its channel by an oxide layer, which is a dielectric. As such, the
current flowing through a CMOS input is virtually zero, and the device is operated mainly
by the voltage applied to the gate, which controls the conductivity of the device channel.
• The input to a TTL circuit is always through the emitter(s) of the input transistor, which
exhibits a low input resistance. The base of the input transistor, on the other hand, is
connected to the Vcc line.
• The low input currents required by a CMOS circuit results in lower power consumption,
which is the major advantage of CMOS over TTL. In fact, power consumption in a CMOS
circuit occurs only when it is switching between logic levels. This power dissipation during
a switching action is known as ‘dynamic power’.
• In a typical CMOS IC, output switching may take about a hundred picoseconds, and may
occur every 10 nanoseconds (or 100 million times per second). Switching an output from one
logic level to another requires the charging and discharging of various load capacitances,
which dissipates power that is proportional to these capacitances and the frequency of
switching.
• TTL devices can drive more power into a load than CMOS. TTL is less sensitive to static-
discharge failure and less expensive. It is also faster.
• Most TTL circuits use a totem pole output circuit, which replaces the pull-up resistor with a
Vcc-side transistor sitting on top of the GND side output transistor. The emitter of the Vcc-
side transistor (whose collector is tied to Vcc) is connected to the collector of the GND-side
transistor (whose emitter is grounded) by a diode. The output is taken from the collector
of the GND-side transistor.

• TTL uses a different type of transistor (bipolar) whereas CMOS uses MOSFETs. FETs do
not have current flowing into the “gate” when static, whereas bipolar do (into the “base”),
so generally this allows them to operate with lower power especially in a stand-by type of
state.
Contd....

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