Page 126 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 7: Standard Integrated Circuits (ICs)

Notes
Figure 7.9: Pull-down Network (PDN)

As an example, here is a NOR gate in NMOS logic. If either input A or input B is high (logic 1,
= True), the respective MOS transistor acts as a very low resistance between the output and the
negative supply, forcing the output to be low (logic 0, = False). When both A and B are high,
both transistors are conductive, creating an even lower resistance path to ground. The only case
where the output is high is when both transistors are off, which occurs only when both A and B
are low, thus satisfying the truth table of a NOR gate:
Table 7.3: Truth Table of NOR Gate

A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0

A MOSFET can be made to operate as a resistor, so the whole circuit can be made with n-channel
MOSFETs only. For many years, this made NMOS circuits much faster than comparable PMOS
and CMOS circuits, which had to use much slower p-channel transistors. It was also easier to
manufacture NMOS than CMOS, as the latter has to implement p-channel transistors in special
n-wells on the p-substrate. The major problem with NMOS (and most other logic families) is that
a DC current must flow through a logic gate even when the output is in a steady state (low in the
case of NMOS). This means static power dissipation, i.e. power drain even when the circuit is
not switching. This is a similar situation to the modern high speed, high density CMOS circuits
(microprocessors etc.) which also has significant static current draw, although this is due to
leakage, not bias. However, older and/or slower static CMOS circuits used for ASICs, SRAM
etc., typically have very low static power consumption.
Also, NMOS circuits are slow to transition from low to high. When transitioning from high to
low, the transistors provide low resistance, and the capacitative charge at the output drains away
very quickly (similar to discharging a capacitor through a very low resistor). But the resistance
between the output and the positive supply rail is much greater, so the low to high transition
takes longer (similar to charging a capacitor through a high value resistor). Using a resistor of
lower value will speed up the process but also increases static power dissipation. However, a
better (and the most common) way to make the gates faster is to use depletion-mode transistors
instead of enhancement-mode transistors as loads. This is called depletion-load NMOS logic.
7.7.4 Important Features of NMOS

• N-MOS is 1/3 of the size of the P-MOS.
• N-MOS is much faster than P-MOS.

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