Page 122 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Unit 7: Standard Integrated Circuits (ICs)

7.6.1 Advantages Notes
• Increased Noise Margin
• Spike Control

• High Noise Threshold Value
7.6.2 Disadvantages

Slow speed due to increased supply voltage resulting in use of high value resistors.
The CMOS settings directly affect the operation of the motherboard. If they
are incorrectly set, the machine may not function very well or may fail to boot
altogether.

Self Assessment

True or False:
1. The DCTL gate is suffering from a phenomenon known as current hogging.

(a) True (b) False
2. The first integrated circuits were created in the late 1948s.
(a) True (b) False

3. The high input currents required by a CMOS circuit results in high power consumption.
(a) True (b) False
4. CMOS circuits were invented by Frank Wanlass of Fairchild Semiconductor in 1963.
(a) True (b) False
5. CMOS chips work with a broader range of power supply voltages.
(a) True (b) False

7.7 NMOS and CMOS Logic Gates

The term ‘Complementary Metal-Oxide-Semiconductor’, or simply ‘CMOS’, refers to the device
technology for designing and fabricating integrated circuits that employ logic using both n- and
p-channel MOSFET’s. CMOS is the other major technology utilized in manufacturing digital
IC’s aside from TTL, and is now widely used in microprocessors, memories, and digital ASIC’s.

The input to a CMOS circuit is always to the gate of the input MOS transistor, which exhibits a
very high resistance. This high gate resistance is due to the fact that the gate of a MOS transistor
is isolated from its channel by an oxide layer, which is a dielectric. As such, the current flowing
through a CMOS input is virtually zero, and the device is operated mainly by the voltage applied
to the gate, which controls the conductivity of the device channel.
The low input currents required by a CMOS circuit results in lower power consumption, which is
the major advantage of CMOS over TTL. In fact, power consumption in a CMOS circuit occurs only
when it is switching between logic levels. This power dissipation during a switching action is known
as ‘dynamic power’. In a typical CMOS IC, output switching may take about a hundred picoseconds,
and may occur every 10 nanoseconds (or 100 million times per second). Switching an output from
one logic level to another requires the charging and discharging of various load capacitances, which
dissipates power that is proportional to these capacitances and the frequency of switching.
Figure 7.7 shows an example of a CMOS circuit – an inverter that employs a p-channel and an
n-channel MOS transistor. A logic ‘1’ Vin voltage at the input would make T1 (p-channel) turn

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