Page 247 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design

Notes This ramp generator can be constructed in a number of different ways. One way might be to use
a D/A converter driven by a simple binary counter. This would generate the staircase waveform
previously discussed and shown in Figure 12.16a. A second method is to use an operational
amplifier (OA) connected as an integrator as shown in Figure 12.33b. For this circuit, if V is a
i
constant, the output voltage is given by the relationship V =(V /RC)t. Since V , R, and C are all
o i i
constants, this is the equation of a straight line that has a slope (V /RC) as shown in Figure 12.33a.
i
Now that we have a way to generate a voltage ramp and we understand its characteristics, let us
return to the converter in Figure 12.32.
We assume that the clock is running continuously and that any input voltage Vx that we wish
to digitize is positive. If it is not, there are circuits that we can use to adjust for negative input
signals. The three decade counters are connected in cascade, and their outputs can be strobed
into three 4-flip-flop latch circuits. The latches are then decoded by seven-segment decoders to
drive the LED displays as units, tens, and hundreds of counts. We can begin a conversion cycle
by depressing the MANUAL RESET switch.
Refer carefully to the logic diagram and the waveforms in Figure 12.32. MANUAL RESET generates
a RESET pulse that clears all the decade counters to 0s and resets the ramp voltage to zero. Since
VX is positive and RAMP begins at zero, the output of the comparator OA, V must be high. This
c
voltage enables the CLOCK gate allowing the clock, CLK, to be applied to the decade counter.
The counter begins counting upward, and the RAMP continues upward until the ramp voltage
is equal to the unknown input V . At this point, time t , the output of the comparator V, goes low,
x
i
thus disabling the CLOCK gate and the counters cease to advance. Simultaneously, this negative
transition on V generates a STROBE signal in the CONTROL box that shifts the contents of the
c
three decade counters into the three 4-flip-flop latch circuits. Shortly thereafter, a reset pulse is
generated by the CONTROL box that resets the RAMP and clears the decade counters to O , and
s
another conversion cycle begins. In the meantime, the contents of the previous conversion are
contained in the latches and are displayed on the seven-segment LEDs.
As a specific example, suppose that the clock in Figure 12.32 is set at 1.0 MHz and the ramp voltage
slope is 1.0 V/ms. Note that the decade counters have the ability to store and display any decimal
number from 000 up to 999. From the beginning of a conversion cycle, it will require 999 clock
pulses (999 µs) for the counters to advance full scale. During this same time period, the ramp
voltage will have increased from 0.0 V up to 999 mV. So, this circuit as it stands will display the
value of any input voltage between 0.0 V and 999 mV.
In effect, we have a digital voltmeter! For instance, if V = 345 mV, it will require 345 clock pulses
x
for the counter to advance from 000 to 345, and during the same time period the ramp will have
increased to 345 mV. So, at the end of the conversion cycle, the display output will read 345—we
supply the units of mille-volts.

One weakness of the single-slope A/D converter is its dependency on an extremely accurate
ramp voltage. This in turn is strongly dependent on the values of R and C and variations of these
values with time and temperature. The dual-slope A/D converter overcomes these problems.

12.9.2 Dual-Slope A/D Converter
The logic diagram for a basic dual-slope A/D converter is given in Figure 12.34. With the exception
of the ramp generator and the comparator, the circuit is similar to the single slope A/D converter
in Figure 12.32. In this case, the integrator forms the desired, ramp—in fact, two different ramps—
as the input is switched first to the unknown input voltage VX and then to a known reference
voltage V . Here is how it works:
r

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