Page 99 - DCAP108_DIGITAL_CIRCUITS_AND_LOGIC_DESIGNS

Digital Circuits and Logic Design

Notes
Multiplex systems were originally implemented to use the spare capacity
available on a line (circuit) for concurrent character or message transmission.

6.1.1 Synthesis of Logic Functions Using Multiplexers
Multiplexers are useful in many practical applications, such as those described above. They
can also be used in a more general way to synthesize logic functions. Consider the example in
Figure 6.6a. The truth table defines the function f = w ⊕ w . This function can be implemented
1
2
by a 4-to-1 multiplexer in which the values of f in each row of the truth table are connected as
constants to the multiplexer data inputs. The multiplexer select inputs are driven by w and w .
2
1
Thus for each valuation of w w , the output f is equal to the function value in the corresponding
2
1
row of the truth table.
The above implementation is straightforward, but it is not very efficient. A better implementation
can be derived by manipulating the truth table as indicated in Figure 6.6b, which allows f to be
implemented by a single 2-to-1 multiplexer. One of the input signals, w in this example, is chosen
1
as the select input of the 2-to-1 multiplexer. The truth table is redrawn to indicate the value of f
for each value of w . When w = 0, f has the same value as input w , and when w = 1, f has the
1
1
2
1
value of w . The circuit that implements this truth table is given in Figure 6.6c. This procedure
2
can be applied to synthesize a circuit that implements any logic function.
Figure 6.6: Synthesis of a Logic Function using Multiplexers
(a) Implementation Using a 4-to-1 Multiplexer (b) Modified Truth Table (c) Circuit
w 2
w 1 w 2 f w 1
0 0 0
0
0 1 1
1
1 0 1 f
1
1 1 0
0
a
()
w w
1 2 f w 1 f
0 0 0
0 w 2
0 1 1
1 w
1 0 1 2
1 1 0
b
()
w 1
w 2
f

()
c

Example: Figure 6.7a gives the truth table for the three-input majority function, and it shows
how the truth table can be modified to implement the function using a 4-to-1 multiplexer. Any
two of the three inputs may be chosen as the multiplexer select inputs. We have chosen w1 and
w2 for this purpose, resulting in the circuit in Figure 6.7b.

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